In the related art, an arbitration unit realizes arbitration to each Direct Memory Access (DMA) channel in a round-robin mode. As shown in FIG. 1, a first hardware module sends to a DMA arbitration unit a DMA request (e.g. transmitting data of address A to address B, and the data volume is 90 megabytes) including data transmission information through a first DMA channel. A second hardware module sends to the DMA arbitration unit a DMA request (e.g. transmitting data of address C to address D, and the data volume is 100 megabytes) including data transmission information through a second DMA channel. The DMA arbitration unit performs round-robin from the first channel from the top down in real time to determine data corresponding to the first channel, and sends to a bus command generator a command for transmitting the data corresponding to the first channel. When round-robin is performed to the second channel, it is determined that data corresponding to the second channel need to be transmitted, and a command for transmitting the data corresponding to the second channel is sent to the bus command generator. When round-robin is performed to a fifth channel, if a Central Processing Unit (CPU) sends a DMA request including data transmission information to the DMA arbitration unit through a third DMA channel, the arbitration unit will not respond to the DMA request of the CPU immediately, and will send to the bus command generator a command for transmitting data of the third channel when the DMA arbitration unit performs round-robin to the third channel in the next round-robin.
After receiving from the DMA arbitration unit the command for transmitting the data of the first channel (the DMA arbitration unit sends the command for transmitting the data of the first channel to the bus command generator for the first time), the bus command generator determines a source address, a target address and the volume of the to-be-transmitted data corresponding to the first channel (for the first channel, address A is the source address, and address B is the target address) and caches them in a bus command queue. After receiving from the bus command queue a data transmission command, a bus controller sends to a data path unit a data acquisition command to indicate the data path unit to acquire from the source address data corresponding to a data identifier. After data from the data path unit is received, the acquired data are written in the target address, wherein the bus command queue is a First In First Out (FIFO) data buffer.
In the process above, provided that data transmission rates corresponding to the first channel, the second channel and the third channel are relatively low, a bus blockage will be caused when the data path unit reaches its upper limit of processing. Therefore, when other hardware modules send DMA requests to the DMA arbitration unit through a fourth channel, the fifth channel and a sixth channel, the DMA arbitration unit will stop processing the DMA requests, which results in a relatively low data transmission efficiency and poor DMA performance.
To sum up, the current method of arbitrating each DMA channel in a round-robin mode and transmitting data according to an arbitration result by a DMA arbitration unit is low in data transmission efficiency and poor in DMA performance.